DocumentCode :
2562315
Title :
Implementing register interlocks in parallel-pipeline, multiple instruction queue, superscalar processors
Author :
Weiss, Shlomo
Author_Institution :
Dept. of Electr. Eng.-Syst., Tel Aviv Univ., Israel
fYear :
1995
fDate :
1995
Firstpage :
14
Lastpage :
21
Abstract :
A dependence for data, control, or resources might cause one instruction to become stalled in a pipeline stage waiting for a preceding instruction to produce a result or release a resource. The pipeline control hardware checks for dependences, and prevents the instruction from going to the next pipeline stage if a dependence occurs. We refer to this hardware as interlock logic. The amount and complexity of the interlock logic required to support a ten+ instruction issue bandwidth is a major concern in the design of the pipeline control hardware. We look specifically at register interlocks in the context of a parallel pipeline with separate dispatch and issue phases-a generalization of the pipeline organization implemented by a number of prominent recent superscalar processors. We describe four implementations of the register interlock logic and a comparison based on the number of logic levels. We also present a high-bandwidth implementation of table-based register renaming
Keywords :
parallel architectures; pipeline processing; queueing theory; reduced instruction set computing; storage management; high-bandwidth implementation; interlock logic; parallel-pipeline multiple instruction queue superscalar processors; pipeline control hardware; pipeline organization; register interlocks; table-based register renaming; Arithmetic; Bandwidth; Clocks; Control systems; Counting circuits; Hardware; Logic design; Pipelines; Reduced instruction set computing; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Performance Computer Architecture, 1995. Proceedings., First IEEE Symposium on
Conference_Location :
Raleigh, NC
Print_ISBN :
0-8186-6445-2
Type :
conf
DOI :
10.1109/HPCA.1995.386559
Filename :
386559
Link To Document :
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