Effectiveness of yield-estimation and reliability-prediction based on wafer test-chip measurements

Studies suggest the use of “dropped in” test chips as an instrument for monitoring the quality of each manufacturing step of VLSI chips, and as a cost-effective procedure for eliminating potentially “bad” wafers. Here, the yield and long-term reliability are estimated on the basis of the test chips manufactured on the same wafer as the fully functional chips. Only wafers accepted based on this preliminary characterization are subjected to a complete MIL-38510 (or equivalent) characterization of all packaged chips. Successful application of this principle, however, depends on several things, such as degree of similarity between the structures on the test chip versus the structures on the fully functional chips, on the number of test chips, their location within the wafer and so on. In particular, it has been found necessary to take into account that the distribution of defects is not purely random, for example there may be a tendency that the defect density varies between the center and the edge of the wafer, and adjacent chips are often found to be statistically dependent. The study presented in this paper seeks to determine the effectiveness of estimating the wafer quality, in particular in terms of wafer yield. A Monte Carlo simulation model has been developed, that allows us to compare yield estimates with “actual” wafer yields, under various scenarios of defect density variation, test structure scaling factor, and test chip sample size and location within the wafer