Custom design in a low-power/high-performance ASIC world

Author

Garibay, Ty ; Reis, Richard

Author_Institution

Austin Design Center, Texas Instrum., Dallas, TX, USA

fYear

2009

fDate

18-20 May 2009

Firstpage

1

Lastpage

2

Abstract

Aggressive design cycle requirements are making it increasingly difficult to deploy custom and even semi-custom design techniques in consumer ASIC´s. However, market requirements continue to push IP implementation teams harder and harder for increased performance and reduced power consumption. Given these two conflicting trends, new design methodologies are required, such that IP design teams can meet market expectations, without the large staffs and long schedules that have traditionally characterized custom design. This presentation reviews several high-ROI methodologies which can be utilized in this design environment to improve implementations without dramatic impact to budgets and schedules.

Keywords

application specific integrated circuits; clocks; industrial property; integrated circuit design; low-power electronics; application specific integrated circuits; grid clock; integrated circuit design; intellectual property; mesh clock; Application specific integrated circuits; Assembly; Clocks; Design methodology; Design optimization; Electronic design automation and methodology; Energy consumption; Instruments; Job shop scheduling; Timing; compiled cache RAMs; grid clock; mesh clock; structured datapath; tiling;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-2933-2

Electronic_ISBN

978-1-4244-2934-9

Type

conf

DOI

10.1109/ICICDT.2009.5166251

Filename

5166251