Parallel Architectures with Small World Network Model

The technology of circuit refinement has achieved a tremendous large-scale integration, so huge VLSI systems have emerged. However, in the huge VLSI systems, various problems, such as latency, power dissipation bottlenecks and clock synchronization of the entire system, must be solved in order to realize a dependable and safe system. Small World Network allows communication between arbitrary nodes where hopping over a small number of nodes is possible in a network with a huge number of nodes. In this paper, our aim is to introduce a parallel architecture with short path communication, featuring a random connection in Small World Network.