Title :
A 0.9 V to 5 V mixed-voltage I/O buffer using NMOS clamping technique
Author :
Wang, Chua-Chin ; Liu, Jen-Wei ; Kuo, Ron-Chi
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
A 0.9 V to 5 V (0.9/1.2/1.8/2.5/3.5/5 V) mixed-voltage I/O buffer with NMOS clamping technique is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 3 times VDD voltage level signal without gate-oxide overstress hazard. Besides, the leakage current effect is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to 140/120/120/120/80/40 Mbps for 5/3.3/2.5/1.8/1.2/0.9 V, respectively, with a given capacitive load of 10 pF.
Keywords :
MOS integrated circuits; buffer circuits; leakage currents; NMOS clamping technique; capacitive load; dynamic gate bias generator; floating N-well circuit; gate drive voltages; gate-oxide overstress hazard; leakage current effect; mixed-voltage I/O buffer; voltage 0.9 V to 5 V; voltage level signal; Circuits; Clamps; Detectors; Hazards; Leakage current; Logic; MOS devices; Protection; Signal generators; Voltage control; I/O buffer; gate-oxide reliability; gate-traking circuit; mixed-voltage-tolerant;
Conference_Titel :
IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-2933-2
Electronic_ISBN :
978-1-4244-2934-9
DOI :
10.1109/ICICDT.2009.5166258
