FIFO design for a high-speed network interface

We address issues in determining FIFO sizes necessary for high-performance, in an integrated high-speed network interface, using a 100 Mbps Fast Ethernet controller as an example. A detailed analytical model is developed which accounts for system design choices, in addition to network parameters such as packet size and rate. The model yields insight into the impact of system parameters, such memory latency and maximum DMA transfer size, on the size of FIFOs required. The model also shows that the worst-case, in terms of receive-FIFO required, is not necessarily when back-to-back minimum size packets are received, but depends on the system parameters such as maximum DMA transfer size. We also study the possibility of FIFO underflows for the transmit direction