DocumentCode :
2563410
Title :
A GaAs vector processor based on parallel RISC microprocessors
Author :
Misko, T.A. ; Rasset, T.L.
Author_Institution :
McDonnell Douglas Astronautics Co., Huntington Beach, CA, USA
fYear :
1988
fDate :
7-12 Feb. 1988
Firstpage :
42583
Lastpage :
811
Abstract :
A vector processor architecture based on the development of a 32-bit microprocessor using gallium arsenide (GaAs) technology has been developed. The McDonnell Douglas vector processor (MVP) will be fabricated completely from GaAs digital integrated circuits. The MVP architecture includes a vector memory of 1 megabyte, a parallel bus architecture with eight processing elements connected in parallel, and a control processor. The processing elements consist of a reduced instruction set CPU (RISC) with four floating-point coprocessor units and necessary memory interface functions. This architecture has been simulated for several benchmark programs including complex fast Fourier transform (FFT), complex inner product, trigonometric functions, and sort-merge routine. The results of this study indicate that the MVP can process a 1024-point complex FFT at a speed of 112 mu s (389 megaflops) while consuming approximately 618 W of power in a volume of approximately 0.1 ft/sup 3/.<>
Keywords :
III-V semiconductors; computerised signal processing; fast Fourier transforms; gallium arsenide; microprocessor chips; parallel architectures; reduced instruction set computing; 32 bits; 32-bit microprocessor; 389 MFLOPS; GaAs; McDonnell Douglas vector processor; benchmark programs; complex fast Fourier transform; complex inner product; digital integrated circuits; floating-point coprocessor; microprocessor chips; parallel RISC microprocessors; parallel bus architecture; reduced instruction set CPU; sort-merge routine; trigonometric functions; vector processor architecture; Central Processing Unit; Coprocessors; Digital integrated circuits; Fast Fourier transforms; Gallium arsenide; Integrated circuit technology; Microprocessors; Process control; Reduced instruction set computing; Vector processors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Aerospace Applications Conference, 1988. Digest., 1988 IEEE
Conference_Location :
Park City, UT, USA
Type :
conf
DOI :
10.1109/AERO.1988.38664
Filename :
38664
Link To Document :
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