Systematic approach of FinFET based SRAM bitcell design for 32nm node and below

Methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves considerations on both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower V_ccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell < 0.1 mum² below 32 nm node.