Title :
Calculating worst-case gate delays due to dominant capacitance coupling
Author :
Dartu, Florentin ; Pileggi, Lawrence T.
Keywords :
Capacitors; Delay lines; Dielectrics; Equations; Integrated circuit noise; Parasitic capacitance; Permission; Predictive models; Semiconductor device noise; Thickness control;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-7803-4093-0
DOI :
10.1109/DAC.1997.597115
