Towards a state synchronization methodology for recovery process after partial reconfiguration of fault tolerant systems

Modern fault tolerant systems implemented into FPGAs integrate very often hardware redundancy together with fault tolerant approaches based on active fault recovery and the system reconfiguration. Space and safety-critical applications are examples of systems where the principles of fault tolerance and recovery techniques have increasing importance. Except of fault-masking behavior and FPGA partial reconfiguration, also the synchronization of reconfigured circuit copy with remaining circuits which are during the recovery process still operating, is an integral part of the recovery process in these systems. The synchronization process is closely related to the system architecture, specific requirements and functionality. Our aim is to propose specific methodology to design and implement the most suitable synchronization procedure for the recovery of target fault tolerant system. In this paper, basic principles of our synchronization methodology are described together with generic architecture for synchronization in fault tolerant systems, which was designed for reconfigurable fault tolerant CAN bus control system. This system and performed experiments are in the paper described as well.