DocumentCode :
2564481
Title :
Data Memory Minimisation For Synchronous Data Flow Graphs Emulated On DSP-FPGA Targets
Author :
Adé, Marleen ; Lauwereins, Rudy ; Peperstraete, J.A.
Author_Institution :
Katholieke Universiteit Leuven
fYear :
1997
fDate :
9-13 June 1997
Firstpage :
64
Lastpage :
69
Keywords :
Computer buffers; Digital signal processing; Emulation; Field programmable gate arrays; Flow graphs; Hardware; Permission; Phase estimation; Pipelines; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
ISSN :
0738-100X
Print_ISBN :
0-7803-4093-0
Type :
conf
DOI :
10.1109/DAC.1997.597118
Filename :
597118
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2564481
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