Mixed digital/analog signal processing for a single-chip 251Q U interface transceiver

Careful partitioning of signal-processing tasks between the analog and digital domains to exploit the strengths of each results in an efficient design of a 2B1Q ISDN basic-rate U-interface single-chip transceiver. This 5-V CMOS device provides transmission across the digital subscriber line at 160 kb/s full duplex, in full compliance with ANSI standard T1.601. The serial 2B+D data from the digital interface is rate-adapted to 160 kb/s and cyclic redundancy check (CRC), maintenance, and control bits are inserted in the digital interface (DIF) section of the circuit. The resulting data stream is then scrambled and 18-b synchronization words are inserted. Conversion to an 80-kHz four-level signal takes place in the line encoder. The transmitter includes a 2B1Q pulse shaper, a five-level fully differential pulse-duration-modulation digital-to-analog (PDM D/A) converter, a third-order transmit filter, and a fully differential line driver. A raised-cosine 78% time-roll-off pulse is stored in the pulse shaper, using a PDM code, at 96 samples per baud. Pulse symmetry allows storage of the first half-pulse only. The back half is generated by a time-mirror circuit. At every baud interval, the current di-bit encodes the pulse front half, while the past di-bit encodes the pulse back half. The two resulting quantities are then combined and provided to a 7.68-MHz five-level PDM D/A converter. Undesirable high-frequency components are eliminated by one pole of low-pass filtering in the D/A converter circuit and two extra poles in the line drive circuit.<>