System, process, and design implications of a reduced supply voltage microprocessor

Author

Allmon, Randy ; Benschneider, B. ; Callander, M. ; Chao, Leon ; Dever, D. ; Farrell, Jay A. ; Fitzgerald, N. ; Grodstein, J. ; Hassoun, Soha ; Hudepohl, L. ; Kravitz, Daniel ; Lundberg, Jonas ; Marcello, R. ; Marino, Silvia ; Pickholtz, J. ; Preston, Rich

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1990

fDate

14-16 Feb. 1990

Firstpage

48

Lastpage

49

Abstract

The system, process, and design implications of converting a microprocessor chip set originally implemented in a 5-V, 1.5- mu m (drawn) CMOS process to one implemented in a 3.3-V, 1.0- mu m (drawn) CMOS process are described. The chip set is 75% faster than the previous generation and comprises a processor chip, a floating-point chip, a cache controller chip, and a clock chip. It operates at 62.5 MHz under worst-case conditions. Micrographs of each design are given. Power and packaging specifications for each chip and the 3.3-V, 1.0- mu m (drawn) process specifications are tabulated. A high-temperature schmoo plot for the CPU chip is also given.<>

Keywords

CMOS integrated circuits; microprocessor chips; storage management chips; 1.0 micron; 3.3 V; CMOS process; cache controller chip; clock chip; floating-point chip; high-temperature schmoo plot; microprocessor chip set; packaging specifications; reduced supply voltage; worst-case conditions; CMOS process; Circuits; Clocks; MOS devices; Microprocessors; Oscillators; Process design; Resistors; Tin; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International

Conference_Location

San Francisco, CA, USA

Type

conf

DOI

10.1109/ISSCC.1990.110123

Filename

110123