Title :
A 90 MHz CMOS RISC CPU designed for sustained performance
Author :
Tanksalvala, D. ; Lamb, John ; Buckley, Mike ; Long, Brenda ; Chapin, S. ; Lotz, J. ; Delano, E. ; Luebs, R. ; Erskine, K. ; McMullen, S. ; Forsyth, M. ; Novak, R. ; Gaddis, T. ; Quarnstrom, D. ; Gleason, C. ; Rashid, Ekbal ; Halperin, Dan ; Sigel, L. ; H
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both commercial and technical multiuser applications. Key performance features include a 3-ns, 32-b adder; low-skew on-chip clock buffers; and cycling off-chip caches at the operating frequency, using industry-standard synchronous static random-access memories (SRAMs). The speeds obtained are comparable to those of many emitter-coupled logic (ECL) implementations. The CPU chip includes the following hardware: integer fetch and execute unit, on-chip split I/D TLBs (translation lookaside buffers) with two-way 64 entries each, control for second-level off-chip TLBs, control for off-chip two-way split I/D writeback caches with single-bit error correction for data, full multiprocessing support hardware, inference for performance analysis and tuning, and a tightly coupled coprocessor interface.<>
Keywords :
CMOS integrated circuits; buffer storage; microprocessor chips; reduced instruction set computing; 140-instruction set; CMOS; I/D writeback caches; RISC CPU; adder; cycling off-chip caches; integer fetch and execute unit; multiprocessing support hardware; multiuser applications; on-chip clock buffers; on-chip split I/D TLBs; single-bit error correction; sustained performance; synchronous static random-access memories; tightly coupled coprocessor interface; translation lookaside buffers; workstation; Clocks; Coprocessors; Error correction; Frequency; Hardware; Logic; Performance analysis; Process design; Reduced instruction set computing; Workstations;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110125
