A 55 ns 4 Mb EPROM with 1-second programming time

Author

Nakamura, Yoshihiko ; Wada, Tomotaka ; Komori, Kenji ; Hagiwara, Tomomichi

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1990

fDate

14-16 Feb. 1990

Firstpage

62

Lastpage

63

Abstract

A 55-ns, 4-Mb (256-kW*16 b) EPROM with a 1-s programming time is described. By use of 0.8- mu m lithography, a memory cell size of 2.8*2.8 mu m/sup 2/ is achieved, resulting in an 8.13*9.27 mm-die. A polycide structure is used to decrease the word line resistance and interconnection resistance, and a lightly doped drain (LDD) structure is used in the peripheral gates of pMOS and nMOS transistors to prevent degradation of characteristics induced by hot carriers. A double-well structure is adopted to improve the characteristics of short-channel pMOS transistors by optimizing the concentration of well regions. The process parameters for this device are summarized. To decrease the word line resistance, the memory array is divided into four planes, with one X-decoder for each pair of planes. This results in a 25% improvement in the access time, with a 10% die size penalty.<>

Keywords

EPROM; MOS integrated circuits; VLSI; integrated memory circuits; 1 s; 4 Mbit; 55 ns; EPROM; X-decoder; access time; double-well structure; hot carriers; interconnection resistance; lightly doped drain; lithography; memory cell size; nMOS; pMOS; peripheral gates; polycide structure; process parameters; programming time; well regions; word line resistance; Degradation; Design optimization; EPROM; Hot carriers; Latches; Lithography; MOSFETs; Microprocessors; Monitoring; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International

Conference_Location

San Francisco, CA, USA

Type

conf

DOI

10.1109/ISSCC.1990.110130

Filename

110130