Title :
A 4 ns BiCMOS translation-lookaside buffer
Author :
Tamura, L. ; Yang, T.-S. ; Wingard, D. ; Horowitz, Mark ; Wooley, B.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
A 64-entry, fully associative translation lookaside buffer (TLB) which has pin-to-pin address translation time of 3.6 ns is described. This translation speed is achieved with a BiCMOS content addressable memory (CAM) and static-random-access-memory (SRAM) arrays that maintain small signal swings throughout the critical translation path.. The TLB has been integrated as a stand-alone chip in a 0.8- mu m BiCMOS technology. The circuit operates from a 5.2-V supply with emitter-coupled-logic (ECL) compatible input and output levels. The power dissipation, excluding the power dissipated in the physical address output buffers, is less than 600 mW.<>
Keywords :
BIMOS integrated circuits; SRAM chips; buffer storage; content-addressable storage; integrated memory circuits; 0.8 micron; 3.6 ns; BiCMOS translation-lookaside buffer; ECL; content addressable memory; critical translation path.; pin-to-pin address translation time; power dissipation; small signal swings; stand-alone chip; static-random-access-memory; Associative memory; BiCMOS integrated circuits; CADCAM; Clocks; Computer aided manufacturing; Latches; Memory management; Phased arrays; Power dissipation; Random access memory;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110132
