A 300 K-circuit ASIC logic family

Author

Petrovick, J. ; Taylor, Russell ; Bertolet, A. ; Chu, A. ; Harroun, T. ; Keyser, F. ; LaMarche, C. ; Pastel, L. ; Richardson, G. ; Worth, B.

Author_Institution

IBM Gen. Technol. Div., Essex Junction, VT, USA

fYear

1990

fDate

14-16 Feb. 1990

Firstpage

88

Lastpage

89

Abstract

A 300 K-circuit ASIC (application-specific-integrated-circuit) family built in a 0.8- mu m four-level-metal single-poly CMOS process is discussed. Wafers consist of p/sup +/ substrate with a p-epitaxial layer and retrograde n-wells. Polysilicon and diffusions are silicided for low resistance. Nominal effective channel length is 0.45 mu m and gate oxides are 120 A. A local interconnect level enhances density. Metal levels 1, 2, and 3 have a contact pitch of 2.4 mu m; metal level 4 has a pitch of 4.8 mu m. All metal lines are aluminum with tungsten vias. Chips are organized as a sea of cells. The standard-cell library consists of 91 combinatorial and sequential elements, available in three performance levels to control delay over a wide range of loads. Three types of embedded array macros are available: fixed custom static random-access memories (SRAMs), growable SRAMs (GRAMs), and growable register arrays (GRAs). Up to 472 full-function signal I/Os are available per chip.<>

Keywords

CMOS integrated circuits; SRAM chips; application specific integrated circuits; cellular arrays; integrated logic circuits; logic arrays; ASIC logic family; combinatorial elements; contact pitch; effective channel length; embedded array macros; fixed custom static random-access memories; four-level-metal single-poly CMOS process; full-function signal I/Os; gate oxides; growable SRAMs; growable register arrays; local interconnect level; p-epitaxial layer; retrograde n-wells; sea of cells; sequential elements; standard-cell library; Application specific integrated circuits; Artificial intelligence; CMOS logic circuits; Delay; Driver circuits; Libraries; Logic circuits; Logic design; Pins; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International

Conference_Location

San Francisco, CA, USA

Type

conf

DOI

10.1109/ISSCC.1990.110142

Filename

110142