BiCMOS circuits for DPCM coders in HDTV systems

For the digital transmission of HDTV signals, special data-reduction techniques have to be used. One of these techniques is predictive coding or differential pulse-code modulation (DPCM). This coding technique removes redundancy from natural pictures without reducing spatial resolution. The critical timing path in these coders is defined by the recursive loop in the kernel. If the latency time of this loop can be made shorter than the clock period of the system (about 20 ns for HDTV), a simple implementation of the coder is possible. It can be shown that by architectural changes the number of components in this loop can be reduced to one latch, one adder, and one quantizer (programmable logic array). Circuit techniques that achieve the required operating speed when implemented in a 2.5- mu m single-metal BiCMOS technology are described.<>