An ultra-high speed GaAs DCFL flip-flop-MCFF (memory cell type flip flop)

Author

Shikata, M. ; Tanaka, K. ; Inokuchi, K. ; Sano, Y. ; Akiyama, M.

Author_Institution

OKI Electr. Ind. Co. Ltd., Tokyo, Japan

fYear

1988

fDate

6-9 Nov. 1988

Firstpage

27

Lastpage

30

Abstract

A novel type of GaAs DCFL (direct-coupled FET logic) static flip-flop named MCFF (memory-cell-type flip-flop) is described. This circuit was implemented as a D-flip-flop and as a T-flip-flop IC (integrated circuit) using 0.5- mu m gate-length GaAs MESFETs fabricated by the advanced self-alignment process technique. An operating data bit rate of 10 Gb/s with a phase margin of 51 degrees was achieved in the D-flip-flop with a power dissipation of 98 mW. The maximum toggle frequency of 16 GHz was obtained in the T-flip-flop with a power dissipation of 48 mW.<>

Keywords

III-V semiconductors; digital integrated circuits; field effect integrated circuits; flip-flops; gallium arsenide; integrated circuit technology; 0.5 micron; 10 Gbit/s; 16 GHz; 48 mW; 98 mW; D-flip-flop; DCFL flip-flop; GaAs; MCFF; MESFETs; T-flip-flop; data bit rate; direct-coupled FET logic; maximum toggle frequency; memory cell type flip flop; phase margin; power dissipation; self-alignment process technique; semiconductors; static flip-flop; ultra high speed flip flops; Bit rate; Circuits; FETs; Gallium arsenide; Inverters; Logic; MESFETs; Master-slave; Power dissipation; Propagation delay;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1988. Technical Digest 1988., 10th Annual IEEE

Conference_Location

Nashville, Tennessee, USA

Type

conf

DOI

10.1109/GAAS.1988.11016

Filename

11016