Title :
A 1 mu A retention 4 Mb SRAM with a thin-film-transistor load cell
Author :
Hayakawa, S. ; Kakumu ; Takeuchi, H. ; Sato, Kiminori ; Ohtani, T. ; Yoshida, Takafumi ; Nakayama, Taiki ; Morita, S. ; Kinugawa, M. ; Maeguchi, K. ; Ochii, K. ; Matsunaga, J. ; Aono, A. ; Noguchi, Keisuke ; Asami, Takuya
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A 1- mu A-retention, 4-Mb SRAM with a thin-film-transistor (TFT) load cell, fabricated in a 0.5- mu m triple-poly-Si (first- and third-level W-polycide) double-Al CMOS technology is described. A 200-fA/b retention current is achieved. utilizing the PMOS-type TFT, in which the n/sup +/ diffusion area of the driver transistor acts as a gate electrode of the TFT. The RAM, which has a built-in voltage down converter (VDC), operates with a 3.3-V supply from a standard 5 V+or-10% external supply. In the battery backup mode, an on-chip external-supply-level sensor disables the VDC, and the retention current of the RAM is reduced to 1 mu A.<>
Keywords :
CMOS integrated circuits; SRAM chips; thin film transistors; 0.5 micron; 1 muA; 3.3 V; PMOS-type TFT; SRAM; Si; TFT load; battery backup mode; built-in voltage down converter; double-Al CMOS technology; external-supply-level sensor; n/sup +/ diffusion area; static RAM; thin-film-transistor; triple polysilicon; Batteries; CMOS technology; Decoding; Driver circuits; Electrodes; MOS devices; Random access memory; Read-write memory; Thin film transistors; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110160
