Behavioral modeling and simulation of jitter and phase noise in fractional-N PLL frequency synthesizer

A methodology is presented for predicting the phase noise and jitter of a fractional-N PLL based frequency synthesizer. Based on the phase/jitter properties extracted from transistor level through simulation, a voltage-domain behavioral model can give phase noise performance of fractional-N PLL frequency synthesizers in system level accurately, while the simulation efficiency is also improved by merging the VCO block operated at the highest frequency into those operated at lower frequency. Comparing to phase-domain simulation, the improved voltage-domain models do a better job of capturing the details of the behavior of the loop, details such as the signal capturing and escaping traces in fractional-N frequency synthesizer.