Title :
Efficient functional verification for mixed signal IP
Author_Institution :
Cadence Design Syst., Inc, San Jose, CA, USA
Abstract :
We describe a methodology for verifying the functional operation of a mixed-signal circuit block to be used in a larger integrated circuit. Methodology requirements are outlined, including: compatibility with digital verification at the chip level, compatibility with circuit analysis at the block level, and compatibility with project schedule and resource availability. The methodology is described with examples on a case-study using a 10/100 Ethernet physical layer implementation. Results from the case study show the benefits of applying the methodology to future mixed-signal design projects.
Keywords :
integrated circuit design; logic testing; mixed analogue-digital integrated circuits; Ethernet physical layer implementation; circuit analysis; digital verification; functional verification; integrated circuit; mixed signal IP; mixed-signal circuit; mixed-signal design; project schedule; resource availability; Analytical models; Application specific integrated circuits; Availability; Circuit analysis; Circuit simulation; Circuit synthesis; Design methodology; Physical layer; Signal analysis; Signal design;
Conference_Titel :
Behavioral Modeling and Simulation Conference, 2004. BMAS 2004. Proceedings of the 2004 IEEE International
Print_ISBN :
0-7803-8615-9
DOI :
10.1109/BMAS.2004.1393982
