A programmable CCD signal processor

Author

Chiang, Ann-Shyn ; Mountain, R. ; Reinold, J. ; LaFranchise, J. ; Gregory, J. ; Lincoln, G.

Author_Institution

MIT Lincoln Lab., Lexington, MA, USA

fYear

1990

fDate

14-16 Feb. 1990

Firstpage

146

Lastpage

147

Abstract

A charge-coupled-device (CCD) signal processor based on a vector-matrix product-computing algorithm is described. The processor is structured to perform the generic weighted-sum operation required in a neural network, and to compute the inner product of two matrices needed for two-dimensional spatial filtering. Used as a neural net processor, the chip provides 2016 programmable interconnections between 144 input nodes and 14 output nodes, performs 2.8-billion arithmetic operations/s and dissipates less than 2 W at a 10-MHz clock rate. The CCD device consists of analog tapped delay lines as input buffers, multiplying D/A converters (MDACs), and on-chip memory for storing the digital weights.<>

Keywords

charge-coupled device circuits; computerised signal processing; digital signal processing chips; neural nets; 10 MHz; 2 W; DSP; analog tapped delay lines; charge-coupled-device; generic weighted-sum operation; inner product; matrices; multiplying D/A converters; neural net processor; on-chip memory; programmable CCD signal processor; programmable interconnections; two-dimensional spatial filtering; vector-matrix product-computing algorithm; Arithmetic; Buffer storage; Charge coupled devices; Clocks; Computer networks; Delay lines; Filtering; Neural networks; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International

Conference_Location

San Francisco, CA, USA

Type

conf

DOI

10.1109/ISSCC.1990.110169

Filename

110169