A 10 b 15 MHz recycling two-step A/D converter

A fully differential CMOS videorate converter whose linearity relies on a binary-weighted capacitor array known to exhibit a 10-b linearity is described. The recycling analog-to-digital converter (ADC) does not have the sampling error found in other two-step or multistep pipelined architectures because it requires only one input sampling per conversion. A single-ended schematic of a digitally corrected ADC is shown. One feature of this architecture is the multiple role of a capacitor-array multiplying digital-to-analog converter (MDAC). One MDAC replaces three functional blocks in a standard two-step architecture: a sample-and-hold amplifier, a residue amplifier, and a DAC. As a result, the proposed ADC does not require precision components other than an MDAC. One conversion is finished in three clock phases.<>