A full fill-factor CCD imager with integrated signal processors

A (64*64) imager that combines simple charge-domain analog signal processors in a parallel, pipelined architecture to realize an integrated signal processor that performs a simple edge detection algorithm in real time is described. With a serial output clock rate of 10 MHz, the signal processor is capable of 1000-frames/s operation. This signal-processing capability is implemented with standard CMOS technology without decreasing the fill factor of the imager, without significantly increasing power dissipation, and with only a 15 % increase in chip area. As a column of image pixel data is shifted simultaneously, local interactions between neighboring column elements are directly performed in parallel. As row values are sequentially clocked through the processor local interactions between neighboring row elements are similarly performed by delay elements. This architecture is able to implement efficiently linear convolutions that are separable and recursively defined. It is also suitable for certain types of nonlinear filtering operations that perform image segmentation a basic machine vision task.<>