Title :
A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode
Author :
Konishi, Yasuo ; Dosaka, Katsumi ; Komatsu, Teruhisa ; Ionue, Y. ; Kumanoya, M. ; Tobita, Y. ; Genjyo, H. ; Nagatomo, Makoto ; Yoshihara, Tatsuhiko
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
Abstract :
A 4-Mb DRAM that has 38-ns RAS (row-address-strobe) access time and a battery-backup (BBU) mode, and retains data with a 44- mu A current requirement is described. The BBU mode is a self-refresh mode. Its power dissipation, however, is reduced in comparison with that of a normal refresh operation. The memory can operate as a standard 4-Mb DRAM, without any timing constraint on CAS (column-address-strobe) and RAS, if the operating cycle does not exceed 16 ms. This approach promises more stable supply at lower cost than specially provided counterparts such as pseudo-SRAMs.<>
Keywords :
DRAM chips; 38 ns; 4 Mbit; 44 muA; CAS; DRAM; RAS; battery back-up; current requirement; operating cycle; power dissipation; row-address-strobe; self-refresh mode; Batteries; Bonding; CMOS process; CMOS technology; Circuits; Packaging; Random access memory; Switches; Testing; Wiring;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110209
