A p-well GaAs MESFET technology

A p-well GaAs MESFET technology that permits the development of precision mixed-mode integrated circuits is discussed. The p- and n-type regions of the structure are formed by implanting Be/sup 9/ and Si/sup 29/, respectively. The potential of the p-well is constrained by connecting it to the source of the MESFET, ensuring that the source-drain junctions never become forward biased. The p-type layers are beneficial in reducing short-channel effects and in improving both control and matching of pinch-off voltages. Because the p-well GaAs MESFET eliminates the long time constant associated with the drain-current transients and the frequency-dependent g/sub ds/, fast-settling GaAs operational amplifiers and comparators free of frequency-dependent hysteresis are possible. Digital circuits with propagation delay and fanout characteristics independent of frequency and logic patterns are also possible. These advantages arise because the constrained p-well effectively shields the device from trap-related charge fluctuations in the substrate.<>