Title :
A 100 MHz 64-tap FIR digital filter in a 0.8 mu m BiCMOS gate array
Author :
Yoshino, Tomonobu ; Davis, Howard ; Shah, Aamer ; Yang, Ping ; Jain, R.
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A 64-tap FIR (finite-impulse-response) digital filter fabricated in a 0.8- mu m, triple-level interconnect, BiCMOS gate-array technology is discussed. The filter has been tested and is fully functional at 100-MHz sampling rate. These results are obtained by combining an optimized architecture and gate-array floor planning with submicron BiCMOS technology. A total design time of one week was achieved using a filter compiler. About two-thirds (49 mm/sup 2/) of the 100 K gate-array core was allocated to the filter. The design is equivalent to about 55 K gates (two-input NAND gates) in complexity and utilizes 76% of the core allocation. The device input/output are 100 K emitter-coupled logic (ECL) compatible. The functional switching waveforms of the master clock, least-significant-bit (LSB) input, and most-significant-bit (MSB) output at 1.00-MHz operating frequency are shown.<>
Keywords :
BIMOS integrated circuits; application specific integrated circuits; digital filters; digital signal processing chips; logic arrays; 0.8 micron; 100 MHz; 64 tap type; BiCMOS gate array; FIR digital filter; finite-impulse-response; floor planning; submicron BiCMOS technology; triple-level interconnect; Added delay; BiCMOS integrated circuits; Clocks; Digital filters; Finite impulse response filter; Pipelines; Propagation delay; Sampling methods;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110227
