Abstract :
Circuit design becomes more and more challenging with the advent of SoC era in that several sepatate chips are to integrated into one chip. Of non-recurrent engineering (NRE) cost, verification takes a main part during entire design flow. Basically, there are two major problems in current verification procedure. This paper describes a new verification environment that incooperates assertion-based technique and firmware to provide a system level verification. Cores of this verification environment are bus functional models, bus protocol monitors, firmware layer software, and a set of checker implmented with TestWizard. We develop a platform to verify the behavior of PCI and PCI-Express devices efficiently. A set of performance evaluation tools are also be developed at the same time. By applying these performances tools, the verification environment helps designers not only verify the circuit function but evaluate the performance.
