DocumentCode
2566526
Title
A 14b 20mW 640MHz CMOS CT /spl Delta//spl Sigma/ ADC with 20MHz Signal Bandwidth and 12b ENOB
Author
Mitteregger, G. ; Ebner, C. ; Mechnig, S. ; Blon, T. ; Holuigue, C. ; Romani, E. ; Melodia, A. ; Melini, V.
Author_Institution
Xignal Technol., Munich
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
131
Lastpage
140
Abstract
A 3rd-order single-loop CT DeltaSigma modulator with a 4b internal quantizer operating at 640MHz achieves 76dB SNR, -78dB THD, and 74dB SINAD in a 20MHz signal bandwidth with an OSR of 16. The modulator operates between 20 to 40MS/S output data rate and dissipates 20mW from a 1.2V supply at 40MS/S. The degradation of stability due to excess loop delay is solved with a quantizer feedback architecture
Keywords
CMOS integrated circuits; delta-sigma modulation; quantisation (signal); 1.2 V; 20 MHz; 20 mW; 640 MHz; CMOS; CT DeltaSigma ADC; ENOB; loop delay; quantizer feedback architecture; Bandwidth; CMOS technology; Clocks; Computed tomography; Delay; Feedback; Resonator filters; Sampling methods; Stability; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696042
Filename
1696042
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