DocumentCode
2566581
Title
A 14mW Multi-bit /spl Delta//spl Sigma/ Modulator with 82dB SNR and 86dB DR for ADSL2+
Author
Kwon, Susanna ; Maloberti, Franco
Author_Institution
Texas Univ., Richardson, TX
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
161
Lastpage
170
Abstract
Analog and digital feedforward swing-reduction techniques optimize the power consumption of this 2nd-order DeltaSigma modulator. The 0.18um CMOS prototype uses 2 telescopic OTAs and 2 ADCs requiring 10 comparators. The technique makes the modulator equivalent to a 4b architecture. The OSR is 33 and the clock frequency is 144MHz
Keywords
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); delta-sigma modulation; digital subscriber lines; operational amplifiers; 0.18 micron; 14 mW; 144 MHz; 82 dB; ADC; ADSL2+; CMOS; DeltaSigma modulator; OSR; OTA; SNR; clock frequency; comparators; feedforward swing reduction; Capacitance; Capacitors; Delay; Delta modulation; Design optimization; Power harmonic filters; Quantization; Sampling methods; Strontium; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696045
Filename
1696045
Link To Document