Title :
A 5.4mW 2-Channel Time-Interleaved Multi-bit /spl Delta//spl Sigma/ Modulator with 80dB SNR and 85dB DR for ADSL
Author :
Lee, Kye-shin ; Kwon, Sunwoo ; Maloberti, Franco
Author_Institution :
Texas Univ., Richardson, TX
Abstract :
A 2nd-order DeltaSigma modulator that obtains low power consumption by 2-channel time-interleaving is described. The main channel requires 2 opamps whereas the second channel does not use any active elements. This structure is robust to channel mismatches and uses a simple clocking scheme. The circuit is integrated in a 0.18mum CMOS process and occupies an active area of 1.1mm2
Keywords :
CMOS integrated circuits; delta-sigma modulation; digital subscriber lines; low-power electronics; operational amplifiers; 0.18 micron; 5.4 mW; ADSL; CMOS process; DeltaSigma modulator; channel mismatches; low power consumption; opamps; CMOS process; Circuits; Clocks; Delta modulation; Energy consumption; Feedback; Filters; MIM capacitors; Quantization; Robustness;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696046
