A 3 ns 1 K*4 static self-time GaAs RAM

Author

Fiedler, A. ; Chun, Jung-Hoon ; Kang, D.

Author_Institution

GigaBit Logic, Newbury Park, CA, USA

fYear

1988

fDate

6-9 Nov. 1988

Firstpage

67

Lastpage

70

Abstract

A GaAs 1 K*4 static self-timed random-access memory (SSTRAM) with input and output latches and internal write-pulse generation has been designed, fabricated, and tested. Fully functional SSTRAMs have been obtained, with a worst-case clock access time (equal to read and write cycle time) of 3.6 ns for a 1.9-W device. This part is manufactured using three levels of interconnect metallization and a novel high-margin enhancement-depletion (HMED) process, and utilizes many innovative circuits.<>

Keywords

III-V semiconductors; field effect integrated circuits; gallium arsenide; integrated circuit technology; integrated memory circuits; random-access storage; 1.9 W; 3.6 ns; 4 kbit; GaAs; HMED; SRAM; SSTRAM; clock access time; high-margin enhancement-depletion; innovative circuits; internal write-pulse generation; latches; multilevel metallisation; operation; semiconductors; static RAM; static self-timed random-access memory; three level metallisation; Automatic testing; Circuit testing; Clocks; Gallium arsenide; Integrated circuit interconnections; Latches; Manufacturing processes; Metallization; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1988. Technical Digest 1988., 10th Annual IEEE

Conference_Location

Nashville, Tennessee, USA

Type

conf

DOI

10.1109/GAAS.1988.11025

Filename

11025