• DocumentCode
    2566653
  • Title

    An 80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC for Digital TV Receivers

  • Author

    Fujimoto, Yasutaka ; Kanazawa, Yuji ; Lore, P. ; Miyamoto, Masayuki

  • Author_Institution
    Sharp, Nara
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    201
  • Lastpage
    210
  • Abstract
    A 4th-order SC DeltaSigma modulator with a 4b quantizer is designed for a low-power direct-conversion receiver SoC for Japanese ISDB-T and European DVB-T. It achieves a 76.3/70.1dB SNDR over a 3.2/4MHz bandwidth with a clock frequency of 80/100MHz. The 1.7mm2 chip, fabricated in a 0.18mum CMOS process draws 13.2/19.1mA from a 1.8V supply. It has a FOM of 0.7/1.64pJ/conversion
  • Keywords
    CMOS integrated circuits; delta-sigma modulation; low-power electronics; quantisation (signal); system-on-chip; television receivers; 0.18 micron; 1.8 V; 13.2 mA; 19.1 mA; 3.2 MHz; 4 MHz; ADC; CMOS process; DeltaSigma; SNDR; digital TV receivers; low power direct conversion receiver SoC; quantizer; Bandwidth; Clocks; Communication standards; Data communication; Delta modulation; Digital TV; Digital multimedia broadcasting; Digital video broadcasting; Multiplexing; TV receivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696049
  • Filename
    1696049
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2566653