Title :
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS
Author :
Meghelli, Mounir ; Rylov, S. ; Bulzacchelli, John ; Rhee, Woogeun ; Rylyakov, A. ; Ainspan, Herschel ; Parker, Brendon ; Beakes, Michael ; Chung, Albert ; Beukema, Troy ; Pepeljugoski, Petar ; Shan, Long ; Kwark, Y. ; Gowda, Suraj ; Friedman, Daniel
Author_Institution :
IBM, Yorktown Heights, NY
Abstract :
A 90nm CMOS 10Gb/s SerDes for chip-to-chip communications over backplanes is presented. To mitigate channel impairments, the RX uses a 5-tap DFE and the TX a 4-tap FIR filter. The IC equalization abilities are evaluated using different type of channels. The power consumption of one (TX, RX) pair and one PLL is 300mW for 1.2Vpp differential TX output swing
Keywords :
CMOS integrated circuits; FIR filters; decision feedback equalisers; phase locked loops; transceivers; 1.2 V; 10 Gbit/s; 300 mW; 4-tap-FFE transceiver; 5-tap-DFE; 90 nm; CMOS; FIR filter; PLL; SerDes; channel impairments; chip to chip communications; integrated circuit equalization; Bandwidth; Clocks; Data communication; Decision feedback equalizers; Delay; Electrostatic discharge; Energy consumption; Interpolation; Packaging; Transceivers;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696051
