DocumentCode :
2566717
Title :
A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control
Author :
Moon, Yongsam ; Ahn, Gijung ; Choi, Hoon ; Kim, Namhoon ; Shim, Daeyun
Author_Institution :
Silicon Image, Sunnyvale, CA
fYear :
2006
fDate :
6-9 Feb. 2006
Firstpage :
233
Lastpage :
242
Abstract :
A multi-rate transceiver incorporating TX slew control with >2times range, PLL with <0.5times loop-filter area using capacitance multiplication, and DeltaSigmaZ-SSCG having 11.7dB peak reduction is designed in 0.13mum CMOS. Occupying 2.33mm2 with TX operable up to 8.5Gb/s, the quad transceiver consumes 386mW from 1.2V supply and has a BER<10-14 at 6Gb/s over an 8m cable with 22dB loss
Keywords :
CMOS integrated circuits; delta-sigma modulation; phase locked loops; transceivers; 0.13 micron; 1.2 V; 22 dB; 386 mW; 6 Gbit/s; 8 m; DeltaSigma-SSCG; PLL; TX slew control; capacitance multiplication; multi-rate CMOS transceiver; quad transceiver; Capacitance; Capacitors; Electromagnetic interference; Filters; Frequency; Jitter; Phase locked loops; Reactive power; Transceivers; Varactors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0079-1
Type :
conf
DOI :
10.1109/ISSCC.2006.1696053
Filename :
1696053
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2566717
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