Title :
A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces
Author :
Prete, E. ; Scheideler, D. ; Sanders, Aric
Author_Institution :
Infineon, Munich
Abstract :
An architecture for next-generation memory interface is demonstrated using 90nm bulk silicon to provide a 2-tap emphasized TX with <19ps jitter at 9.6Gb/s. The circuit uses a programmable PLL to track jitter up to 200MHz. The transceiver consumes 100mW from a 1V supply
Keywords :
CMOS integrated circuits; clocks; jitter; low-power electronics; phase locked loops; transceivers; 1 V; 100 mW; 9.6 Gbit/s; 90 nm; CMOS; jitter; memory interfaces; programmable PLL; transceiver; Bandwidth; Circuits; Clocks; Detectors; Filters; Jitter; Phase detection; Phase locked loops; Power system reliability; Transceivers;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696055
