DocumentCode :
2566756
Title :
A 7ns/850 mW GaAs 3 Kb SRAM fully operative at 75 degrees C
Author :
Makino, Hiroshi ; Matsue, Shuichi ; Noda, Minoru ; Tanino, Noriyuki ; Takano, Satoshi ; Nishitani, Kazuo ; Kayano, Shimpei
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
fYear :
1988
fDate :
6-9 Nov. 1988
Firstpage :
71
Lastpage :
74
Abstract :
The authors describe a GaAs 1 K*4 static random-access memory (SRAM) which has been designed using a novel circuit technology to reduce the scattering and the temperature dependence of the access time. To reduce the subthreshold leakage current in the access transistors of the unselected memory cells, the baselines connected to the unselected memory cells were raised from the ground level. The 4-Kb SRAM was fabricated using 1.0- mu m self-aligned MESFETs with buried p-layers beneath the FET regions. A maximum address access time of 7 ns and a power dissipation of 850 mW were obtained for the galloping test pattern at 75 degrees C. Little change in the address access time was observed over 0 to 75 degrees C.<>
Keywords :
III-V semiconductors; field effect integrated circuits; gallium arsenide; integrated circuit technology; integrated memory circuits; random-access storage; 0 to 75 C; 1 micron; 4 kbit; 7 ns; 850 mW; GaAs; SRAM; address access time; buried p-layers; galloping test pattern; novel circuit technology; operation; power dissipation; self-aligned MESFETs; semiconductors; static random-access memory; temperature dependence; Circuits; FETs; Gallium arsenide; MESFETs; Power dissipation; Random access memory; Scattering; Subthreshold current; Temperature dependence; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1988. Technical Digest 1988., 10th Annual IEEE
Conference_Location :
Nashville, Tennessee, USA
Type :
conf
DOI :
10.1109/GAAS.1988.11026
Filename :
11026
Link To Document :
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