K-2 High-performance and low-Power SRAMs design in nano-scale CMOS technology

Summary form only given. Static random access memory (SRAM) is key to today´s high-performance and low-power VLSI system design. Among various embedded memory technologies, SRAM is able to provide the highest performance while maintaining low standby power consumption. As Moore´s law drives the CMOS technology feature size well below 100 nm regime, there are many new technology and design challenges facing today´s SRAM development, including cell stability scaling and power management. In this presentation, the state-of-the-art CMOS technology scaling will be first examined. Key scaling challenges along with technology innovations such as uniaxial strain Si technology will be discussed. Then, the scaling of the SRAM cell design will be evaluated in light of the technology scaling. Various design techniques, e.g., the use of dynamic multi-VCC, in mitigating the scaling difficulties in read stability and write margin will be presented. Power reduction techniques will also be discussed from both process and design perspectives, including transistor design and use of dynamic sleep transistors. Design implementation based on the state-of-the-art CPUs will also be presented.