Title :
A Power-Efficient High-Throughput 32-Thread SPARC Processor
Author :
Leon, Ana Sonia ; Shin, Jinuk Luke ; Tam, K.W. ; Bryg, W. ; Schumacher, Frank ; Kongetira, P. ; Strong, A.
Author_Institution :
SUN Mircrosystems, Sunnyvale, CA
Abstract :
The first generation of Niagara SPARC processors implements a power-efficient multi-threading architecture to achieve high throughput with minimum hardware complexity. The design combines eight 4-threaded 64b cores, a high-bandwidth crossbar, a shared 3MB L2 Cache and four DDR2 DRAM interfaces. The 90nm 378mm2 die consumes 63W at 1.2GHz. Memory design techniques to support the high bandwidth are also discussed
Keywords :
DRAM chips; cache storage; microprocessor chips; system buses; 1.2 GHz; 63 W; 90 nm; DDR2 DRAM interface; L2 cache interface; Niagara SPARC processors; memory design; power-efficient multi-threading architecture; Clocks; Delay; Frequency; Pipelines; Registers; Semiconductor device measurement; Sun; Temperature measurement; Throughput; Yarn;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696060
