Title :
A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache
Author :
Rusu, Stefan ; Tam, Simon ; Muljono, Harry ; Ayers, David ; Chang, Joana
Author_Institution :
Intel, Santa Clara, CA
Abstract :
A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm2 die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes
Keywords :
cache storage; microprocessor chips; 1 MByte; 16 Mbyte; 65 nm; L2 cache; L3 cache; dual-core multi-threaded processor; leakage reduction modes; Circuits; Clocks; Copper; Delay; MOS devices; Packaging; Pins; Power dissipation; Voltage; Yarn;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696062
