Title :
A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support
Author :
Golden, M. ; Arekapudi, S. ; Dabney, G. ; Haertel, M. ; Hale, S. ; Herlinger, L. ; Kim, Youngjae ; McGrath, Kevin ; Palisetti, V. ; Singh, Monika
Author_Institution :
Adv. Micro Devices, Sunnyvale, CA
Abstract :
A microprocessor featuring 2 Hammer cores and an on-chip DDR2 memory controller implements Pacifica architectural support for virtualization. It is fabricated in a 90nm triple-Vt partially-depleted SOI process with 9 layers of copper interconnect. The chip achieves a clock frequency of 2.6GHz at 1.35V while dissipating 95W
Keywords :
DRAM chips; copper; integrated circuit interconnections; microprocessor chips; system-on-chip; 1.35 V; 2.6 GHz; 90 nm; 95 W; DDR2 memory controller; Pacifica architectural support; copper interconnect; microprocessor; partially-depleted SOI process; virtualization; Clocks; Control systems; Copper; Frequency; Logic arrays; Microprocessors; Repeaters; Routing; Signal design; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696063
