A 64B CPU Pair: Dual- and Single-Processor Chips

Author

Cohen, E.B. ; Rohrer, N.J. ; Sandon, P. ; Canada, M. ; Lichtenau, C. ; Ringler, M. ; Kartschoke, P. ; Floyd, Raymond E. ; Heaslip, J. ; Ross, M. ; Pflueger, T. ; Hilgendorf, R. ; McCormick, Patrick ; Salem, Gerard ; Connor, John ; Geissler, S. ; Thygesen,

Author_Institution

IBM, Essex Junction, VT

fYear

2006

fDate

6-9 Feb. 2006

Firstpage

333

Lastpage

342

Abstract

Two Powertrade-architecture 64b microprocessor chips are fabricated in 90nm dual strained-silicon SOI technology. The dual-processor chip has split clock domains and power planes, 1 MB L2 cache per core and a shared processor interconnect bus. The single-processor chip shares the dual´s basic core and cache design

Keywords

cache storage; integrated circuit interconnections; microprocessor chips; silicon-on-insulator; 1 MByte; 90 nm; L2 cache; Powertrade-architecture; clock domains; dual strained-silicon SOI technology; dual-processor chip; microprocessor chips; power planes; shared processor interconnect bus; single-processor chip; Circuit noise; Clocks; Copper; Frequency; Latches; Microprocessors; Phase locked loops; Resistors; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0079-1

Type

conf

DOI

10.1109/ISSCC.2006.1696064

Filename

1696064

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2566927