DocumentCode
2567026
Title
A novel dynamic scheduling algorithm of data hazard for embedded processor
Author
Lu, Jiajing ; Zhou, Xiaofang ; Wang, Junyu
Author_Institution
Fudan Univ., Shanghai
fYear
2007
fDate
22-25 Oct. 2007
Firstpage
28
Lastpage
31
Abstract
To solve the data hazard of embedded processor, this paper designs a dynamic scheduling algorithm to improve the pipeline efficiency, which only increases one single-instruction buffer and some combination logic. In FFT and FIR experiment, the algorithm leads to the decrease of the pipeline conflict to 100% and 75% respectively. There is 8.2% additional area of the whole processor.
Keywords
dynamic scheduling; embedded systems; microprocessor chips; pipeline processing; FFT; FIR experiment; combination logic; data hazard; dynamic scheduling algorithm; embedded microprocessor; pipeline technique; single-instruction buffer; Algorithm design and analysis; Dynamic scheduling; Embedded system; Hazards; Heuristic algorithms; Microprocessors; Pipelines; Process design; Scheduling algorithm; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-4244-1132-0
Electronic_ISBN
978-1-4244-1132-0
Type
conf
DOI
10.1109/ICASIC.2007.4415559
Filename
4415559
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