DocumentCode
2567067
Title
A microarchitecture of clustered superscalar processor
Author
Bing, Yang ; Zhigang, Mao ; Chuhui, Gan
Author_Institution
Harbin Inst. of Technol., Harbin
fYear
2007
fDate
22-25 Oct. 2007
Firstpage
36
Lastpage
39
Abstract
Superscalar processor requires many of high ports and large on-chip structures to extract ILP in applications. And those components are often laid on the critical path, consume huge power and limit the scalability of superscalar. Clustered microarchitecture is an attractive alternative to large monolithic superscalar designs due to their potential for dealing with many problems faced in modern microprocessor design. In this paper, a microarchitecture of clustered superscalar processor with distributed rename, issue, registerfile, execute, and commit logic is proposed and described in detail.
Keywords
logic design; microprocessor chips; parallel architectures; system-on-chip; ILP extraction; clustered microarchitecture; instruction level parallelism; large on-chip structures; registerfile; superscalar processor; CMOS technology; Clocks; Communication networks; Delay; Frequency; Microarchitecture; Processor scheduling; Registers; Scalability; VLIW; Clustered Microarchitecture; Superscalar Processor;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-4244-1132-0
Electronic_ISBN
978-1-4244-1132-0
Type
conf
DOI
10.1109/ICASIC.2007.4415561
Filename
4415561
Link To Document