DocumentCode :
2567114
Title :
Implementation of Hardware IP in a System Level Environment
Author :
Blanchard, Yves
Author_Institution :
ESYCOM, Univ. Paris-Est, Noisy-le-Grand, France
fYear :
2009
fDate :
15-17 May 2009
Firstpage :
182
Lastpage :
186
Abstract :
In this paper we describe a methodology to do rapid hardware prototyping of a part of a digital signal processing system described in Simulink. It explains the main technical problems when trying to go to hardware from a pure functional description and the solutions proposed to solve them. The methodology is applied on a proven model, from the architecture co-simulation, to the real hardware implementation in the system model.
Keywords :
digital signal processing chips; field programmable gate arrays; performance evaluation; Simulink; digital signal processing system; hardware IP; rapid hardware prototyping; system level environment; Clocks; Computational modeling; Digital signal processing; Field programmable gate arrays; Filters; Hardware design languages; Mathematical model; Prototypes; Radar applications; Radar signal processing; DSP; ESL; FPGA; HIL; IP; Simulink; hardware; prototyping;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
2009 International Conference on Signal Processing Systems
Conference_Location :
Singapore
Print_ISBN :
978-0-7695-3654-5
Type :
conf
DOI :
10.1109/ICSPS.2009.6
Filename :
5166771
Link To Document :
بازگشت