• DocumentCode
    2567253
  • Title

    A 16Mb MRAM with FORK Wiring Scheme and Burst Modes

  • Author

    Iwata, Yoshiyuki ; Tsuchida, Kensei ; Inaba, Takaaki ; Shimizu, Yukiyo ; Takizawa, R. ; Ueda, Yuzuru ; Sugibayashi, Tadahiko ; Asao, Y. ; Kajiyama, Tomoko ; Hosotani, K. ; Ikegawa, S. ; Kai, Takafumi ; Nakayama, Makoto ; Tahara, S. ; Yoda, Hidehiko

  • Author_Institution
    Toshiba, Yokohama
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    477
  • Lastpage
    486
  • Abstract
    A 16Mb MRAM based on 0.13mum CMOS and 0.24mum MRAM process achieves a 34ns asynchronous access and 100MHz synchronous operation, compatible with pseudo-SRAM for mobile applications. By implementation of FORK wiring scheme, the cell efficiency is raised to 39.9% and the disturb robustness of half-selection state is improved
  • Keywords
    CMOS integrated circuits; magnetic storage; magnetoresistive devices; mobile communication; random-access storage; wiring; 0.13 micron; 0.24 micron; 100 MHz; 16 Mbit; 34 ns; CMOS; FORK wiring scheme; MRAM; asynchronous access; burst modes; half selection state; mobile applications; pseudo-SRAM; synchronous operation; Clocks; Driver circuits; Magnetic tunneling; National electric code; Random access memory; Switches; Voltage; Wires; Wiring; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696080
  • Filename
    1696080
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2567253