DocumentCode
2567287
Title
A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput
Author
Micheloni, Rino ; Ravasio, R. ; Marelli, A. ; Alice, E. ; Altieri, V. ; Bovino, A. ; Crippa, L. ; Di Martino, E. ; D´Onofrio, L. ; Gambardella, A. ; Grillea, E. ; Guerra, Gilberto ; Kim, Dongkyu ; Missiroli, C. ; Motta, I. ; Prisco, A. ; Ragone, G. ; Roma
Author_Institution
STMicroelectronics, Agrate Brianza
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
497
Lastpage
506
Abstract
A 4Gb 2b/cell NAND flash memory designed in a 90nm CMOS technology incorporates a 25MHz BCH ECC architecture, correcting up to 5 errors over a flexible data field (1B to 2102B). Two alternative Chien circuits are used depending on the number of errors (1 to 5) thus minimizing latency time. ECC area overhead is less than 1%
Keywords
CMOS memory circuits; NAND circuits; embedded systems; flash memories; 25 MHz; 36 Mbit/s; 90 nm; CMOS technology; Chien circuits; NAND flash memory; embedded 5b BCH ECC; latency time; system read throughput; Buffer storage; Costs; Digital audio players; Error correction; Error correction codes; Hardware; Microcontrollers; Polynomials; Throughput; Universal Serial Bus;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696082
Filename
1696082
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