Author :
Micheloni, Rino ; Ravasio, R. ; Marelli, A. ; Alice, E. ; Altieri, V. ; Bovino, A. ; Crippa, L. ; Di Martino, E. ; D´Onofrio, L. ; Gambardella, A. ; Grillea, E. ; Guerra, Gilberto ; Kim, Dongkyu ; Missiroli, C. ; Motta, I. ; Prisco, A. ; Ragone, G. ; Roma
Abstract :
A 4Gb 2b/cell NAND flash memory designed in a 90nm CMOS technology incorporates a 25MHz BCH ECC architecture, correcting up to 5 errors over a flexible data field (1B to 2102B). Two alternative Chien circuits are used depending on the number of errors (1 to 5) thus minimizing latency time. ECC area overhead is less than 1%
Keywords :
CMOS memory circuits; NAND circuits; embedded systems; flash memories; 25 MHz; 36 Mbit/s; 90 nm; CMOS technology; Chien circuits; NAND flash memory; embedded 5b BCH ECC; latency time; system read throughput; Buffer storage; Costs; Digital audio players; Error correction; Error correction codes; Hardware; Microcontrollers; Polynomials; Throughput; Universal Serial Bus;
