DocumentCode
2567411
Title
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme
Author
Kyu-Hyoun Kim ; Uksong Kang ; Hoe-Ju Chung ; Duk-Ha Park ; Woo-Seop Kim ; Young-Chan Jang ; Moonsook Park ; Hoon Lee ; Jin-young Kim ; Jung Sunwoo ; Hwan-Wook Park ; Hyun-Kyung Kim ; Su-Jin Chung ; Jae-Kwan Kim ; Hyung-Seuk Kim ; Kee-Won Kwon ; Young-Taek
Author_Institution
Samsung Electron., Hwasung
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
527
Lastpage
536
Abstract
A 288Mb deca-data rate SDRAM with an I/O error-detection scheme is developed. Deca-data rate is proposed to include CRC for the higher data-rate beyond 5Gb/s/pin using a conventional DRAM process. Several techniques, including an area-efficient cell array consisting oftwo6F2 cells are adopted to enhance the core cycle speed. Measurement results show that the chip has a peak read or write bandwidth of 6.4GB/S and row-cycle time (tRC) of 9.6ns with a 1.6V supply
Keywords
DRAM chips; error detection; 1.6 V; 288 Mbit; 8 Gbit/s; 9.6 ns; CRC; I-O error detection; SDRAM; area-efficient cell array; core cycle speed; deca-data rate; Clocks; Consumer electronics; Cyclic redundancy check; Frequency; Logic; Network servers; Random access memory; SDRAM; Sun; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696089
Filename
1696089
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