a new type of high-performance low-power low clock-swing TSPC flip-flop

Author

Hu, Yingbo ; Li, Zhaolin ; Zhou, Runde

Author_Institution

Tsinghua Univ., Beijing

fYear

2007

fDate

22-25 Oct. 2007

Firstpage

130

Lastpage

133

Abstract

A new type of pulse-triggered true single phase clock (TSPC) flip-flop with low threshold voltage clock transistor and its several improved structures are proposed for high-performance low-power applications. Due to low clock-swing and double-edge triggering, the power consumption of the clock network is estimated to reduce by 78%. HSPICE simulation with 0.18 mum CMOS technology shows that their delay, power dissipation and PDP are reduced by 20~44%, 40~56% and 61~72% respectively, when compared with the existing Low-Swing Clock Double-Edge Triggered Flip-Flop (LSDFF).

Keywords

CMOS logic circuits; SPICE; circuit simulation; clocks; flip-flops; low-power electronics; pulse circuits; CMOS technology; HSPICE simulation; clock network; double-edge triggering; high-performance low-power applications; low clock-swing TSPC flip-flop; power consumption; power dissipation; pulse-triggered true single phase clock flip-flop; threshold voltage clock transistor; CMOS technology; Circuit simulation; Clocks; Delay; Energy consumption; Flip-flops; Frequency; Power dissipation; Pulse generation; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2007. ASICON '07. 7th International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4244-1132-0

Electronic_ISBN

978-1-4244-1132-0

Type

conf

DOI

10.1109/ICASIC.2007.4415584

Filename

4415584